1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device.
2. Related Art
A higher level of integration has been generally required for conventional bipolar transistors and bipolar complementary metal oxide semiconductor (BiCMOS) transistors, resulting in progressing miniaturizations of devices. A trench-type collector section is employed for the bipolar collector section to prevent a diffusion in a collector N+ buried layer, allowing higher levels of the miniaturizations. On the other hand, miniaturizations are also progressed in contact sizes, and thus contacts having smaller diameter but larger depth are required to be formed. The contact of the trench type collector is generally required to be formed to have larger depth by the additional depth of the trench, and thus a process that is capable of providing formations of contacts with higher dimensional accuracy without causing a deviation in the characteristics of the obtained devices is required.
A typical BiCMOS transistor having a trench type collector is described in Japanese Patent Laid-Open No. H11-17,040 (1999). A method for manufacturing such BiCMOS transistor will be described in reference to FIG. 6A to FIG. 6C. First of all, as shown in FIG. 6A, a bipolar transistor having a trench type collector and a complementary metal oxide semiconductor (CMOS) transistor are formed on a p-type silicon substrate 101. A depth of the trench of the collector from the substrate surface is selected to be within a range of from 400 to 500 nm.
The bipolar transistor includes an N+ collector region 104, an N+ emitter region 112, a P-type base region 111 and a P+ graft base 108, which are formed on an N-well region 102. The N+ collector region 104 is provided to a bottom of the trench formed in a P-type silicon substrate 101. Further, an emitter polysilicon 119 is coupled to the N+ emitter region 112.
A CMOS transistor is composed of an N-channel field effect transistor (FET) and a P-channel FET. The N-channel FET includes an N+ source drain 107 and an N-type lightly doped drain (LDD) layer 110, which are formed in the P-well region 103, and a gate oxide film 113, a gate polysilicon 114 and a gate electrode 115, which are formed on the P-type silicon substrate 101. The P-channel FET includes a P+ source drain 106 and a P-type LDD-layer 109, which are formed in the P-well region 102, and the gate oxide film 113, the gate polysilicon 114 and the gate electrode 115, which are formed in the P-type silicon substrate 101.
Surfaces of the above-described N+ collector region 104, the P+ graft base 108, the N+ source drain 107, the P+ source drain 106 and the gate electrode 115 are silicidized to form silicide layers 121. Further, the bipolar transistor, the N-channel FET and the P-channel FET are isolated from each other by an element isolation oxide film 105.
A nitride film 122 having a thickness of about 50 to 100 nm and an interlayer insulating film 123 having a thickness of about 500 nm are formed on the P-type silicon substrate 101, which is provided with the above-described bipolar transistors and the CMOS transistors.
Next, as shown in FIG. 6B, a resist 124 is applied on the entire surface thereof. Subsequently, as shown in FIG. 6C, an opening 126 for a collector contact, an opening 125 for an emitter contact, an opening 127 for a base contact and an opening 128 for a CMOS contact are simultaneously formed by a mask-patterning and an etch processes. As described above, the contact section of the BiCMOS transistor having the trench type collector can be obtained.
Other related art documents include Japanese Patent Laid-Open No. H11-265,953 (1999), in addition to the above-described Japanese Patent Laid-Open No. H11-17,040.
However, the present inventor found out the subjects described below.
When an etch process is performed to form the opening 126 for the collector contact in the manufacturing process illustrated in FIG. 6A to FIG. 6C, the openings for other contacts (i.e., the opening 125 for the emitter contact, the opening 127 for the base contact and the opening 128 for the CMOS contact) are excessively etched by at least the depth of the trench. Such excessive etch causes a roughened surface of the contact bottom, resulting in an increased variation in the characteristics of the semiconductor devices.